Conventionally, there is known a semiconductor package incorporating a semiconductor device mounted on a wiring board. FIG. 1 is a cross-sectional view illustrating a part of a conventional semiconductor package. With reference to FIG. 1, a semiconductor package 300 has a semiconductor device 400 and a wiring board 500. The semiconductor device 400 has a semiconductor substrate 410, electrode pads 420, and connection terminals 430.
A semiconductor integrated circuit (not illustrated in the figure) or the like is formed on the semiconductor substrate 410. For example, the semiconductor substrate 410 is made of silicon. The connection terminals 430 are formed on the respective electrode pads 420 in order to serve as electrodes. Solder bumps may be used as the connection terminals 430.
The wiring board 500 includes an insulation layer 530, a wiring layer 540 and a solder-resist layer 550. In the wiring board 500, the wiring layer 540 is formed on the insulation layer 530, and the solder-resist layer 550, which has aperture parts 550x, is formed on the insulation layer 530. For example, the wiring layer 540 is formed of copper (Cu) or the like. The insulation layer 530 may be formed of, for example, an epoxy resin, a glass epoxy (epoxy resin impregnated glass cloth), etc.
The connection terminals 430 of the semiconductor device 400 are electrically connected to the wiring layer 540 of the wiring board 500 at positions exposed by the aperture parts 550x of the solder resist layer 550. The above-mentioned semiconductor package structure is disclosed in, for example, Japanese Laid-Open Patent Applications No. 2008-153340 and No. 2009-166773.
If a glass epoxy is used to form the insulation layer 530, the thermal expansion coefficient of the insulation layer 530 is about 18 ppm/° C. On the other hand, if silicon is used to form the semiconductor substrate 410, the thermal expansion coefficient of the semiconductor substrate is about 3 ppm/° C. Thus, there is a large difference in thermal expansion coefficient between the insulation layer 530 and the semiconductor substrate 410. When heat is applied to the semiconductor package 300, expansion of the wiring board 500 is much larger than expansion of the semiconductor substrate 410. Thereby, a stress is generated in the joining parts (connection terminals 430) between the semiconductor package 300 and the wiring board 500. Thus, there is a problem in that a crack may be generated at an interface between each of the connection terminals 430 and the wiring layer 540 or in portions of the semiconductor substrate 410 near the connection terminals 430.